The invention relates to semiconductor product test technology, and more particularly, to a method and system of gating rule synchronization for semiconductor device/product testing.
A conventional semiconductor factory typically includes the requisite fabrication tools to process semiconductor wafers for a particular purpose, such as photolithography, chemical-mechanical polishing, or chemical vapor deposition. During manufacture, the semiconductor wafer passes through a series of process steps performed by various fabrication tools. For example, in the production of an integrated semiconductor product, the semiconductor wafer passes through up to 600 process steps. The cost of such automated production is greatly influenced by how well and efficiently the manufacturing process can be monitored or controlled, so that the ratio of defect-free products to the overall number of products manufactured (i.e., yield ratio) achieves the greatest possible value. The individual process steps, however, are subject to fluctuations and irregularities, which in the worst case may mean, for example, the defect of a number of chips or the entire wafer. Therefore, each individual process step must be carried out as stably as possible in order to ensure an acceptable yield after the completed processing of a wafer.
Circuit probing (CP) testing systems/methods have been used in a variety of semiconductor fabrication processes for acquiring yield data. A test program is provided by a user or an operator for performing a CP test on a particular semiconductor product. The test program describes a test flow including multiple test items, and the test items are typically optimally arranged to reduce CP test time. A CP test station then follows the predefined test flow to sequentially probe all dies on a wafer to determine whether a die is good or bad. After completing the entire CP test, results of test attributes such as yield values, quantities of good dies, repairable dies, power short dies and the like, for wafers, wafer lots or semiconductor products, are acquired. Test results are subsequently carried into so-called gating rules to generate final advisories such as acceptance, scrap, hold for analysis and the like, for wafers, wafer lots or semiconductor products.
During manufacturing, the same type of semiconductor products may be tested by different labs or outsourcing test partners. In the past, gating rules in different labs or outsourcing test partners were created or refreshed manually. It has often been argued that final test result advisories for the same type of semiconductor products may be inconsistent due to inconsistencies in gating rule versions. Such gating rule version inconsistencies are often associated with delay refreshing of the up-to-date version or mistyping. Similar limitations are also occurred in in-line testing, wafer acceptance testing (WAT) or other semiconductor device/product testing. Therefore, a need exists for a system and method of semiconductor test management, thereby generating consistent final advisories.